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11th IEEE International Conference on Electronics, Circuits and Systems.
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Microprocessors: Bypass the power wall (at least for a while)
Uri Weiser
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Summary and Short Outline:
Staying within Microprocessor power envelope, becomes a major design obstacle in the design
of future high-end Microprocessors.
A new paradigm should be introduced to enable continues rapid performance improvement (Moore's law).
This talk will introduce a solution that was carved without breaking the law of physics. The solution
will reach better performance by narrowing the application range. The performance power curves and parameter
will be presented.
Short Biography:
Uri Weiser
Uri Weiser received his B.Sc and M.Sc degrees in Electrical Engineering from the Technion,
Israel Institute of Technology, Haifa, Israel in 1970 and 1975 respectively. He received his Ph.D in
Computer Science from the University of Utah, Salt Lake City, in 1981.
Dr. Weiser joined Intel in 1988. Since then he held various positions at Intel among them:
Director of Intel s processor s strategy, Co-manger of Austin Design Center, Director of Streaming
architecture and more. Uri initiated the PentiumŪ processor concept definition, feasibility study
and performance simulator, drove the definition of Intel's MMX technology architecture, co-invented
the "Trace-Cache" concept, the "Streaming data concepts", "Dynamic tuning", and others.
Prior to his career at Intel, Dr. Weiser worked for the Israeli Department of Defense (RAFAEL) from 1970 to
1984, as Research and System Engineer. His next position was with National Semiconductor Design Center, Israel
from 1984 to 1988, leading the design of National's NS32532 Microprocessor.
Dr. Weiser became an Intel Fellow in 1996 and got the IEEE Fellow title in 2002 "for contributions to
Computer Architecture". He got the Distinguish Fellow of the Electrical Engineering Department, Technion
in 2004.
Dr. Weiser holds an Adjunct Associate Professor position at the Technion IIT, he is an Associate Editor
of IEEEMicro Magazine and of Architecture Letters.
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From LC Filters to Filters-on a-Chip: A Technological Odyssey.
George S. Moschytz
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Summary and Short Outline:
The beginning of the evolution of circuits and systems from discrete-component breadboards to integrated
circuit chips goes back more than forty years. One of the last holdouts in this development was that of
frequency-selective inductor-capacitance (LC) filters, because the three-dimensionality of inductors defied
integration on a chip. The fact that continuous-time frequency-selective filters can be integrated today,
as part of so-called mixed-mode systems on a chip, is the result of decades of development and experimentation
in an effort to substitute the electromagnetic resonance effect by inductorless active circuits. That this
is today possible on-chip is the culmination of numerous ingenious developments ranging from the early
thin-film and thick-film hybrid active-RC filters, to digital and switched-capacitor filters, to today's
on-chip-integrated, continuous-time, active RC filters. The long odyssey from then to now involved extraordinary
theoretical and technological developments that will be described briefly in this talk. It will be shown that
although this development is not yet over, today's filters-on-a-chip far exceed anything that could have been
dreamt of forty years ago.
Short Biography:
George S. Moschytz
George S. Moschytz (M.65-SM.77-F.78) received the E.E. Diploma and the Ph.D. degree from the Swiss
Federal Institute of Technology (ETH), Zurich, in 1958 and 1962, respectively. From 1960 to 1962,
he was with RCA Laboratories, Zurich. From 1963 to 1972, he was with Bell Laboratories, Holmdel, NJ,
where he developed and later supervised methods of designing hybrid-integrated active RC filters and
silicon-integrated logic circuits. From 1973 till 2001 he was Professor of Network Theory and Signal
Processing and Director of the Signal and Information Processing Laboratory at ETH in Zurich. In 2001
he joined the Bar-Ilan University in Israel, where he is head of a new Department for Electrical and
Computer Engineering. He has authored and co-authored more than 250 papers in the field of network
theory, active and switched-capacitor filter and network design, and sensitivity theory, holds numerous
patents, and is author and co-author of over ten books in these and related areas. His present interests
are analog, digital, switched-capacitor, switched-current, and adaptive filters, cellular neural networks
and wavelets for signal processing, and the application of signal processing techniques to medical problems
and bio-signals. Prof. Moschytz is Past-President of the IEEE Swiss Chapter on Digital Communication Systems
and a Member of the Swiss Electrotechnical Society.
From 1981 to 1982, he was President of the Swiss Section of the IEEE and served several terms in the Adcom
of the IEEE Circuits and Systems Society. He has been on the
Editorial Board of the Proceedings of the IEEE and was an Associate Editor of the IEEE Circuits and Systems
Magazine. He was on the Board of Governors of the IEEE Circuits and Systems Society and was President of the
Society in 1999. He is an elected member of the Swiss Academy of Engineering Sciences, winner of the Best
Paper Award (for a paper on active filter design using tantalum thin-film technology), winner of the IEEE
CAS Education Award, and has been awarded the IEEE Millnnium Medal, the IEEE Circuits and Systems Society
Golden Jubilee Medal, and is a member of Eta Kappa Nu.
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Nanometer Era: 90-nm/65-nm Design Technologies and Beyond
Peter (Chung-Yu) Wu
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Summary and Short Outline:
Moore's Law applies to scaling of silicon chips into the Nanometer Era. It will steadily continue into
sub-10nm regime. This talk will address research and development details in 90-nm and 65-nm technology
nodes with advanced data from world-leading foundries such as TSMC, UMC, and academic institutions. Design
issues and emerging solutions for (A) analog and mixed-signal designs, (B) memory design, and (C) digital
ASIC design will be presented. Key issues such as power consumption, design-for-manufacturability, yield
enhancement, will be addressed. Recent developments in non-silicon nano-devices will also be described.
A closer look into 45-nm technology node and beyond will be presented.
When the modern CMOS technology was scaled to the 90 nm node by breaking the "100 nm brick wall" a few years
ago, the Nanometer Era for silicon chips began. In the Nanometer Era, there are numerous challenges and
opportunities in the research fields of process technologies, devices, circuits, systems, and electronic
design automation (EDA). According to Moore's Law, nano-CMOS mass-production technology will continue to
advance till around 2020 where sub-10-nm technology node could be reached. Then non-silicon nanostructures
will take over afterward. Currently, world-leading foundries such as TSMC and UMC have provided mature 130-nm
and 90-nm technologies. They are preparing 65-nm technology for mass production. Moreover, advanced research
on 45-nm technology and beyond is extensively conducted. Key technology developments from the foundries will
be highlighted.
In the post-silicon areas, the device/structure portfolio has many interesting targets including carbon-nanotube,
quantum-dot, spintronics, molecular electronics, nano-bionics, single electronics, etc. The grand challenges
are:
(1) Reliable signal input/output and interconnection for nano-devices /
nanostructures;
(2) Stable, reproducible, and low-cost nanofabrication process for
mass production with reasonable yield;
(3) New nanoelectronic circuits, systems, architectures, and design
methodologies for nano-integration;
(4) Verification, testing, and packaging methods for nano-system chips;
(5) Fundamental quantum physics in the atomic or molecule level.
At the 90-nm node of CMOS, the power supply voltage is round 0.9 V. In the year of 2016 or sooner, the 22 nm
node will be reached with the use of 0.4 V supply voltage. Despite the complicated device characteristics
involving quantum effects at all sub-65 nm nodes, the grand challenges for silicon nanoelectronics are in
five major aspects: (1) Interconnect modeling and designing: Interconnect occupies over 75% of signal delay
at 90 nm or smaller nodes and requires efficient modeling techniques and revolutionary chip design methodology;
(2) Ultra-low-power (ULP) low-voltage(LV) but high-speed high-frequency analog/digital IPs: Sub-1 V ULP LV GHz
analog/digital intellectual properties (IPs) which can migrate over 3 or more technology generations without
substantial redesign efforts are required; (3) Programmability in IP/whole-chip design and verification:
Highly programmable IPs and System-on-Chips (SoCs) are needed to avoid the expensive masks/chips redone and
increase the design flexibility; (4) Embedded software to make SOCs meet future needs in many major intelligent
applications; (5) Fast design cycles: Can we design an 100-billion-transistor SOC within 100 days or less?
The great impacts of the above design challenges on (A) analog and mixed-signal design, (B) memory design,
(C) digital ASIC design, and (D) EDA will be described. The current development status of IC design industry
in Taiwan and worldwide will be presented with detailed data. Finally, perspectives will be given.
Short Biography:
Peter (Chung-Yu) Wu
Dr. Peter (Chung-Yu) Wu (1998 IEEE Fellow) is Centennial Chair Professor and also Dean of EECS College at
National Chiao Tung University. He serves as VP-Conferences for 2004 -2005, and was a BoG member in IEEE
CAS Society in 2003. He was General Chair of 1994 IEEE APCCAS Conference. Dr. Wu served as Guest Editor of
Aug. 1997 Multimedia Special Issue for IEEE Trans on CSVT, as Associate Editor for Trans. on CAS-Part II,
Trans. on VLSI Systems, and Trans. on Multimedia. He currently serves as CAS Editor for IEEE Circuits and
Devices Magazine. Dr. Wu is the founding Chair of Technical Committee on Nanoelectronics and Giga-scale
Systems. He served as Chair of Neural Technical Committee, as Chair of Multimedia Technical Committee.
He is CAS Representative to IEEE Neural Networks Society. In regional activities area, Dr. Wu served as
CAS Taipei Chapter Chair, and IEEE Taipei Section Chair. In 2000-2001, Dr. Wu served as a Distinguished
Lecturer in IEEE CAS Society.
Dr. Wu is a recipient of IEEE Third Millennium Medal, a Fellow of IEEE, and also a U.S. Fulbright Scholar.
He is a member of Eta Kappa Nu and Phi Tau Phi Honorary Scholastic Societies. He served as a Semester-Full
Professor in Fall 2003 and as Adjunct International Professor since Spring 2004 for the ECE Department at
University of Illinois, Urbana.
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