BGU_LOGO

Ben-Gurion University of the Negev
Faculty of Engineering Sciences
Department of Electrical and Computer Engineering


Field Programmable Gate
Array (FPGA) Lab


Advanced Computer Laboratory (36114693)


 

Main Page


Download experiments:

Experiment


Datasheets application notes and white paper

SignalTap II

Advanced Topics

Boards

ByteBlaster


Tutorials

VHDL

Verilog HDL

 

Forums:

ALTERA Forum

 

Manufactor's site:

Altera

 

HighLearn

 

  1. The FPGA experiment presented advanced topics in FPGA field, the HDL languages concept and to Altera's Quartus II environment.
  2. The students have to use two development environments - Quartus II and ModelSim with one of these languages: Verilog HDL, VHDL or Altera design objects. The SignalTab and Timing simulations tools will be observed deeply.

 

  1. The recent experiment specification is updated at: http://www.ee.bgu.ac.il/~adcomplab/announcement.htm
  1. Tutorials about Verilog HDL and VHDL can be download form the menu in the left.
  1. Tutorials about Quartus and ModelSim can be found in the software itself.
  1. Students who choose to specialize in Android can choose to do a final Android project. In order to do this, the students have to send their own idea for this project to this e-mail: adcomplab@ee.bgu.ac.il, and wait for an approval for their project. Only then they can start working on it.

Good Luck!

 

This page was built by Nati Shaked, 2003